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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tpl7407la slrs073a ? may 2017 ? revised may 2018 tpl7407la 30-v 7-channel low side driver 1 1 features 1 ? 600-ma rated drain current (per channel) ? cmos pin-to-pin improvement of 7-channel darlington array (for example: uln2003a) ? power efficient (very low v ol ) ? less than 4 times lower v ol at 100 ma than darlington array ? very low output leakage < 10 na per channel ? extended ambient temperature range: t a = ? 40 c to +125 c ? high-voltage outputs 30 v ? compatible with 1.8-v to 5-v microcontroller and logic interface ? internal free-wheeling diodes for inductive kick- back protection ? input pull-down resistors allows tri-stating the input driver ? input rc-snubber to eliminate spurious operation in noisy environment ? inductive load driver applications ? esd protection exceeds jesd 22 ? 2-kv hbm, 500-v cdm ? available in 16-pin soic and tssop packages 2 applications ? inductive loads ? relays ? unipolar stepper & brushed dc motors ? solenoids & valves ? leds ? logic level shifting ? gate & igbt drive 3 description the tpl7407la is a high-voltage, high-current nmos transistor array. this device consists of seven nmos transistors that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. the maximum drain-current rating of a single nmos channel is 600 ma. new regulation and drive circuitry added to give maximum drive strength across all gpio ranges (1.8 v ? 5 v).the transistors can be paralleled for higher current capability. the tpl7407la key benefit is its improved power efficiency and lower leakage than a bipolar darlington implementation. with the lower v ol the user is dissipating less than half the power than traditional relay drivers with currents less than 250 ma per channel. device information (1) part number package (pins) body size (nom) tpl7407lapw tssop (16) 5.00 mm 4.40 mm tpl7407lad soic (16) 9.90 mm 3.91 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. simple application schematic productfolder tpl7407la in3 in4 out1out2 out3 out4 in5in6 in7 gnd out5out6 out7 com in1in2 1.8 v logic 24 v 1.8 v logic c com m v sup copyright ? 2017, texas instruments incorporated support &community tools & software technical documents ordernow
2 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ..................................... 4 6.2 esd ratings ............................................................ 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 switching characteristics .......................................... 5 6.7 typical characteristics .............................................. 6 7 detailed description .............................................. 7 7.1 overview ................................................................... 7 7.2 functional block diagram ......................................... 7 7.3 feature description ................................................... 7 7.4 device functional modes .......................................... 7 8 application and implementation .......................... 9 8.1 application information .............................................. 9 8.2 typical application .................................................. 11 9 power supply recommendations ...................... 14 10 layout ................................................................... 14 10.1 layout guidelines ................................................. 14 10.2 layout example .................................................... 14 10.3 thermal considerations ........................................ 15 11 device and documentation support ................. 16 11.1 receiving notification of documentation updates 16 11.2 community resources .......................................... 16 11.3 trademarks ........................................................... 16 11.4 electrostatic discharge caution ............................ 16 11.5 glossary ................................................................ 16 12 mechanical, packaging, and orderable information ........................................................... 16 4 revision history changes from original (may 2017) to revision a page ? added d package in the device information table, pin configuration and functions section, and thermal information table ..................................................................................................................................................................... 1
3 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 5 pin configuration and functions d and pw package 16-pin soic and tssop top view pin functions pin i/o description name no. com 9 ? supply pin that must be tied to 6.5 v or higher for proper operation (see the power supply recommendations section for more information) gnd 8 ? ground pin in(x) 1 i gpio inputs that drives the outputs "low" (or sink current) when driven "high" 2 3 4 5 6 7 out(x) 10 o driver output that sinks currents after input is driven "high" 11 12 13 14 15 16 in1 in2 in3 in4 in5 in6 in7 16 out1 15 out2 14 out3 13 out4 12 out5 11 out6 10 out7 gnd 9 com ldo emf clamp emf clamp emf clamp emf clamp emf clamp emf clamp emf clamp 1 2 3 4 5 6 7 8
4 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to the gnd/substrate pin, unless otherwise noted. (3) maximum power dissipation is a function of t j (max), ja , and t a . the maximum allowable power dissipation at any allowable ambient temperature is p d = (t j (max) ? t a )/ ja . operating at the absolute maximum t j of 150 c can affect reliability. (4) the package thermal impedance is calculated in accordance with jesd 51-7. 6 specifications 6.1 absolute maximum ratings at 25 c free-air temperature (unless otherwise noted) (1) min max unit v out pins out1-out7 to gnd voltage ? 0.3 32 v v ok output clamp diode reverse voltage (2) ? 0.3 32 v v com com pin voltage (2) ? 0.3 32 v v in pins in1-in7 to gnd voltage (2) ? 0.3 30 v i ds continuous drain current per channel (3) (4) 600 ma i ok output clamp current 500 ma i gnd total continuous gnd-pin current ? 2 a t j operating virtual junction temperature ? 40 150 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. manufacturing with less than 500-v hbm is possible with the necessary precautions. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. manufacturing with less than 250-v cdm is possible with the necessary precautions. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 500 6.3 recommended operating conditions over operating temperature range min max unit v out out1 ? out7 pin voltage for recommended operation 0 30 v v com com pin voltage range for full output drive 6.5 30 v v il in1- in7 input low voltage ("off" high impedance output) 0.9 v v ih in1- in7 input high voltage ("full drive" low impedance output) 1.5 v t a operating free-air temperature ? 40 125 c i ds continuous drain current 0 500 ma (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tpl7407la unit tssop (pw) soic (d) 16 pins 16 pins ja junction-to-ambient thermal resistance 113.1 88 c/w jctop junction-to-case (top) thermal resistance 46.5 47.6 c/w jb junction-to-board thermal resistance 58.6 45.5 c/w jt junction-to-top characterization parameter 7 14.9 c/w jb junction-to-board characterization parameter 58 45.3 c/w
5 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) during production testing, device is tested under short duration, therefore t a = t j . 6.5 electrical characteristics t j = ? 40 c to +125 c; typical values at t a = 25 c (1) parameter test conditions min typ max unit v ol (v ds ) out1- out7 low-level output voltage v in 1.5 v i d = 100 ma 210 450 mv i d = 200 ma 430 900 v il in1- in7 low-level input voltage i d = 5 a 0.9 v v ih in1- in7 high-level input voltage i d = 100 ma 1.5 v i out(off) (i ds_off ) out1- out7 off-state leakage current v out = 24v, v in 0.9v 10 500 na v f clamp forward voltage i f = 200 ma 1.4 v i in(off) in1- in7 off-state input current v inx = 0 v v out = 30 v 500 na i in(on) in1- in7 on state input current v inx = 1.5 v ? 5 v 10 a i com static current flowing through com pin v com = 6.5 v ? 30 v 17 30 a 6.6 switching characteristics typical values at t a = 25 c parameter test conditions min typ max unit t plh propagation delay time, low- to high-level output v inx 1.65 v, vpull-up = 24 v, rpull-up = 48 ? 350 ns t phl propagation delay time, high- to low-level output v inx 1.65 v, vpull-up = 24 v, rpull-up = 48 ? 350 ns c i input capacitance v i = 0, f = 100 khz 5 pf
6 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.7 typical characteristics figure 1. v ol (v ds ) figure 2. flyback diode forward voltage at 25 c figure 3. pw package maximum collector current vs duty cycle at 25 c figure 4. pw package maximum collector current vs duty cycle at 70 c figure 5. d package maximum collector current vs duty cycle at 25 c figure 6. d package maximum collector current vs duty cycle at 70 c output drain current i ds (ma) v ol (v) 0 100 200 300 400 500 0 0.4 0.8 1.2 1.6 2 2.4 d001 -40c 25c 125c duty cycle maximum current per channel (a) 0 20% 40% 60% 80% 100% 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 d008 n = 1 n = 2 n = 3 n = 4 n = 5 n = 6 n = 7 v f (v) i f (ma) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 50 100 150 200 250 300 350 400 450 500 d002 duty cycle maximum current per channel (a) 0 20% 40% 60% 80% 100% 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 d005 n = 1 n = 2 n = 3 n = 4 n = 5 n = 6 n = 7 duty cycle maximum current per channel (a) 0 20% 40% 60% 80% 100% 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 d007 n = 1 n = 2 n = 3 n = 4 n = 5 n = 6 n = 7 duty cycle maximum current per channel (a) 0 20% 40% 60% 80% 100% 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 d006 n = 1 n = 2 n = 3 n = 4 n = 5 n = 6 n = 7
7 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7 detailed description 7.1 overview this device has proven ubiquity and versatility across a wide range of applications. this is due to its integration of 7 low side nmos transistors that are capable of sinking up to 600 ma and wide gpio range capability. the tpl7407la comprises seven high voltage, high current nmos transistors tied to a common ground driven by internal level shifting and gate drive circuitry. the tpl7407la offers solutions to many interface needs, including solenoids, relays, lamps, small motors, and leds. applications requiring sink currents beyond the capability of a single output may be accommodated by paralleling the outputs. the tpl7407la also enables pin to pin replacement with legacy 7 channel darlington pair implementations. this device can operate over a wide temperature range ( ? 40 c to +125 c). 7.2 functional block diagram 7.3 feature description each channel of the tpl7407la consists of high power low side nmos transistors driven by level shifting and gate driving circuitry. the gate drivers allow for high output current drive with a very low input voltage, meaning full operation with low gpio voltages. in order to enable floating inputs a 1-m pull-down resistor exists on each channel. another 50-k resistor exists between the input and gate driving circuitry. this exists to limit the input current whenever there is an over voltage and the internal zener clamps. it also interacts with the inherent capacitance of the gate driving circuitry to behave as an rc snubber to help prevent spurious switching in noisy environment. in order to power the gate driving circuitry an ldo exists. see the power supply recommendations section for further detail on this circuitry. the diodes connected between the output and com pin is used to suppress kick-back voltage from an inductive load that is excited when the nmos drivers are turned off (stop sinking) and the stored energy in the coils causes a reverse current to flow into the coil supply. 7.4 device functional modes 7.4.1 inductive load drive when the com pin is tied to the coil supply voltage, the tpl7407la is able to drive inductive loads and suppress the kick-back voltage via the internal free wheeling diodes. 7.4.2 resistive load drive when driving a resistive load, a pull-up resistor is needed in order for the tpl7407la to sink current and for there to be a logic high level. the com pin must be supplied 6.5 v for full functionality. com out(1-7) in(1-7) 1m 50 k ovp regulation circuitry driver
8 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated device functional modes (continued) 7.4.3 on state input current the current into the inx pins is defined in the electrical characteristics table for input voltages from 1.5 v to 5 v. at higher voltages, this leakage increases, and the input current can be estimated using the approximate clamp voltage for the ovp diode, 6.4 v. equation 1 shows how to approximate input current for input voltages greater than 6.4 v: i in(on) = v in / 1m + (v in - 6.4v) / 50k where ? v in is the input voltage ? 1 m is the input pull-down resistance ? 50 k is the input series resistance ? 6.8 v is the approximate clamp voltage for the ovp diode (1)
9 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tpl7407la is typically used to drive a high voltage and/or current peripheral from an mcu or logic device that cannot tolerate these conditions. the following design is a common application of the tpl7407la, driving inductive loads. this includes motors, solenoids & relays. each load type can be modeled by what's seen in figure 9 . 8.1.1 unipolar stepper motor driver figure 7. stepper motor driver schematic figure 7 shows an implementation of the tpl7407la for driving a uniploar stepper motor. the unconnected input channels can be used for other functions. when an input pin is left open the internal 1-m ? pull down resistor pulls the respective input pin to gnd potential. for higher noise immunity use an external short across an unconnected input and gnd pins. the com pin must be tied to the supply of whichever inductive load is being driven for the driver to be protected by the free-wheeling diode. tpl7407la in3 in4 out1out2 out3 out4 in5in6 in7 gnd out5out6 out7 com in1in2 phase_c phase_b phase_d motor phase_a v sup optional c com motor control pulses (1.8 v to 5 v) copyright ? 2017, texas instruments incorporated
10 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) for more information on this application, see the stepper motor driving with peripheral drivers (driver ics) application report. 8.1.2 multi-purpose sink driver figure 8. multi-purpose sink driver schematic when configured as per figure 8 , the tpl7407la may be used as a multi-purpose driver. the output channels may be tied together to sink more current. the tpl7407la can easily drive motors, relays & leds with little power dissipation. com must be tied to highest load voltage, which may or may not be same as inductive load supply. tpl7407la in3 in4 out1out2 out3 out4 in5in6 in7 gnd out5out6 out7 com in1in2 1.8 v logic 24 v 1.8 v logic c com m v sup copyright ? 2017, texas instruments incorporated
11 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.2 typical application a common application for the tpl7407la is driving inductive loads such as relays, solenoids, and unipolar stepper motors. figure 9. inductive load driver schematic tpl7407la in3 in4 out1out2 out3out4 in5in6 in7 gnd out5out6 out7 com in1in2 1.8 v logic 12 v 12 v 1.8 v logic c com simultaneous operation is limited or enabled by relay resistance, coil voltage and temperature copyright ? 2017, texas instruments incorporated
12 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical application (continued) 8.2.1 design requirements for this design example, use the parameters listed in table 1 as the input parameters. table 1. design parameters design parameter example value gpio voltage 1.8 v, 3.3 v or 5 v coil supply voltage 6.5 v to 30 v number of channels 7 output current (r coil ) 20 ma to 300 ma per channel c com 0.1 f duty cycle 100% 8.2.2 detailed design procedure when using the tpl7407la in a coil driving application, determine the following: ? input voltage range ? temperature range ? output & drive current ? power dissipation 8.2.2.1 ttl and other logic inputs the tpl7407la input interface is specified for standard 1.8 v through 5 v cmos logic interface and can tolerate up to 30 v. at any input voltage the output drivers is going to be driven at its maximum when vcom is greater than or equal to 6.5 v. 8.2.2.2 input rc snubber the tpl7407la features an input rc snubber that helps prevent spurious switching in noisy environments. connect an external 1 k ? to 5 k ? resistor in series with the input to further enhance the tpl7407la ? s noise tolerance. 8.2.2.3 high-impedance input drivers the tpl7407la features a 1-m ? input pull-down resistor. the presence of this resistor allows the input drivers to be tri-stated. when a high-impedance driver is connected to a channel input the tpl7407la detects the channel input as a low level input and remains in the off position. the input rc snubber helps improve noise tolerance when input drivers are in the high-impedance state. 8.2.2.4 drive current the coil current is determined by the coil voltage (v sup ), coil resistance & output low voltage (v ol ) as shown in equation 2 . i coil = (v sup - v ol )/r coil (2) 8.2.2.5 output low voltage the output low voltage (v ol ) is drain to source (v ds ) voltage of the output nmos transistors when the input is driven high and it is sinking current and can be determined by the specifications section or figure 1 .
13 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.2.3 application curve figure 10 was generated with tpl7407la driving an omron g5nb relay -- v in = 5 v; v sup = 12 v & r coil = 2.8 k figure 10. output response with de-activation of coil (turnoff)
14 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9 power supply recommendations the com pin is the power supply pin of this device to power the gate drive circuitry. while a bypass capacitor on this pin is recommended for sensitive power supplies, it is not required for proper operation of the device. the com pin supply ensures full drive potential with any gpio above 1.5 v. the gate drive circuitry is based on low voltage cmos transistors that can only handle a max gate voltage of 7 v. an integrated ldo reduces the com voltage of 6.5 v to 30 v to a regulated voltage of 5.3 v. though 6.5 v minimum is recommended for vcom, the part still functions with a reduced com voltage that has a reduced gate drive voltage and a resulting higher rdson. 10 layout 10.1 layout guidelines thin traces can be used on the input due to the low current logic that is typically used to drive the tpl7407la. care must be taken to separate the input channels as much as possible, so as to eliminate cross-talk. thick traces are recommended for the output, in order to drive whatever high currents that may be needed. wire thickness can be determined by the trace material's current density and desired drive current. since all of the channels currents return to a common ground, it is best to size that trace width to be very wide. some applications require up to 2 a. since the com pin only draws up to 30 a, thick traces are not necessary. 10.2 layout example figure 11. package layout tpl7407la in3in4 out1out2 out3out4 in5in6 in7 gnd out5out6 out7 com in1in2 c com gnd only needed for fluctuating supplies gnd copyright ? 2017, texas instruments incorporated
15 tpl7407la www.ti.com slrs073a ? may 2017 ? revised may 2018 product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10.3 thermal considerations the number of coils driven is dependent on the coil current and on-chip power dissipation. the number of coils driven can be determined by figure 3 or figure 4 . for a more accurate determination of number of coils possible, use equation 3 to calculate tpl7407la on-chip power dissipation p d : where ? n is the number of channels active together ? v oli is the out i pin voltage for the load current i li . this is the same as v ce(sat) (3) in order to guarantee reliability of tpl7407la and the system, the on-chip power dissipation must be lower than or equal to the maximum allowable power dissipation (p d(max) ) dictated by below equation equation 4 . where ? t j(max) is the target maximum junction temperature ? t a is the operating ambient temperature ? ja is the package junction to ambient thermal resistance (4) it is recommended to limit rhe tpl7407la ic ? s die junction temperature to less than 125 c. the ic junction temperature is directly proportional to the on-chip power dissipation. 10.3.1 improving package thermal performance ja value depends on the pc board layout. an external heat sink and/or a cooling mechanism, like a cold air fan, can help reduce ja and thus improve device thermal capabilities. refer to ti ? s design support web page at www.ti.com/thermal for a general guidance on improving device thermal performance. n d oli li i 1 p v i = = ? ( ) j(max) a (max) ja t t pd - = q
16 tpl7407la slrs073a ? may 2017 ? revised may 2018 www.ti.com product folder links: tpl7407la submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 11 device and documentation support 11.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 24-may-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tpl7407ladr active soic d 16 2500 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 tpl7407lad TPL7407LAPWR active tssop pw 16 2000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 tpl747la (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 24-may-2018 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tpl7407ladr soic d 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 q1 TPL7407LAPWR tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 16-may-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tpl7407ladr soic d 16 2500 364.0 364.0 27.0 TPL7407LAPWR tssop pw 16 2000 364.0 364.0 27.0 package materials information www.ti.com 16-may-2018 pack materials-page 2

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